Integrated circuits often operate based on a system clock signal that may be used to synchronize operation of components of the system. As faster operation of the system is desired, a clock frequency of the system clock will typically be increased. The operability of the integrated circuits should scale with the higher clock frequency to ensure error free operation at the higher speed.
An example of a circuit that is clocked at the frequency of a system clock is a read data path that provides data from, for example, a memory array to be output. FIG. 1 illustrates a read data path 100. The read data path 100 includes a multiplexer 112 coupled to a data cache register (DDC) and a databus 110. The DDC is segmented into two portions DDC0 and DDC1, each of which provides read data to a respective input of the multiplexer 112 in response to a clock signal CLK. The read data is provided from the DDC to the multiplexer 112 in an interleaved manner. The multiplexer 112 is controlled by the CLK signal to switch back and forth between providing read data from DDC0 and providing read data from DDC1 to a clocked data register 130, e.g., READ FIFO 130, over the databus 110. Read data is clocked into (and out of) the clocked data register 130 responsive to the CLK signal.
Operation of the read data path 100 is described with reference to FIG. 2A. At time T0 a rising edge of the CLK signal clocks DDC0 and at time T1, after a propagation delay of DDC0, data “A” is provided (e.g. output) from DDC0 to the multiplexer 112. A falling edge of the CLK signal at time T2 clocks DDC1 and also controls the multiplexer 112 to couple the input from DDC0 to the databus 110 to provide read data A to the clocked data register 130. At time T3 read data “1” is output from DDC1 (delay relative to the falling edge of the CLK signal caused by DDC propagation delay) and at time T4, after a propagation delay of the multiplexer 112 and the databus 110, read data A arrives at the clocked data register 130. The data register is clocked by the rising edge of the CLK signal at time T5 (i.e., the next rising edge of the CLK signal following the rising edge that clocked DDC0 to release data A) to capture (e.g. clock in) read data A. Data 1 is provided by the multiplexer 112 over the databus 110 to the clocked data register 130 in response to the rising edge of the CLK signal at time T5. After the propagation delay of the multiplexer 112 and the data bus 110, data 1 arrives at the clocked data register 130 at time T6 and is captured by the falling edge of the CLK signal at time T7. Data captured by the clocked data register 130 are later output (e.g. clocked out) responsive to the CLK signal.
FIG. 2B illustrates operation of the read data path 100 with a CLK signal having twice the clock frequency of the CLK signal of FIG. 2A. At time T0 a rising edge of the 2X CLK signal clocks DDC0 and at time T2, after a propagation delay of the DDC0, data “A” is output to the multiplexer 112. Due to the higher frequency of the 2X CLK signal, a falling edge of the CLK signal occurs at time T1 before data A is provided to the multiplexer 112. The multiplexer 112 is controlled by the falling edge of the 2X CLK signal at time T2 to provide data A to its output, and as a result, when data A is output by DDC0 data A is provided by the multiplexer 112 to the databus 110. Due to the propagation delay of the multiplexer 112 and the databus 110, data A is not provided to the clocked data register 130 until time T5. The rising edge of the 2X CLK signal at time T3, however, is the edge designated to latch data A (i.e., the rising edge after the rising edge clocking DDC0) into the clocked data register 130. Consequently, unknown data on the databus at time T3 and not data A will be captured (e.g. latched) into the clocked data register 130. Similarly, data 1 provided by DDC1 in response to the falling edge of the 2X CLK signal at time T1 will also not be correctly captured by the falling edge of the 2X CLK signal at T5.
As shown by FIGS. 2A and 2B, although the read data path 100 may be operable for a clock signal having a first frequency, it may not be operable when the clock signal is scaled to a higher second frequency.